diff -x CVS -x .svn -x .git -x .hg -x '*~' -x '.#*' -x autom4te.cache -urpN packages/devs/flash/amd/am29xxxxxv2/v2_0_92/cdl/flash_am29xxxxx_v2.cdl packages/devs/flash/amd/am29xxxxxv2/v2_0_92/cdl/flash_am29xxxxx_v2.cdl
--- packages/devs/flash/amd/am29xxxxxv2/v2_0_92/cdl/flash_am29xxxxx_v2.cdl	2007-05-29 15:24:09.000000000 +0100
+++ packages/devs/flash/amd/am29xxxxxv2/v2_0_92/cdl/flash_am29xxxxx_v2.cdl	2018-11-10 05:02:25.294107038 +0000
@@ -157,6 +157,17 @@ cdl_package CYGPKG_DEVS_FLASH_AMD_AM29XX
                      loop."
     }
 
+    cdl_option CYGNUM_DEVS_FLASH_AMD_AM29XXXXX_V2_ERASE_DELAY {
+	display		"Delay between polls while erasing"
+	flavor		data
+	default_value	0
+	legal_values	0 to 0x7fffffff
+	description "The timings of certain processors and flash devices mean that
+                     a short delay may be required between each poll as it is erased.
+                     This option defines that delay in terms of iterations of a delay
+                     loop."
+    }
+    
     cdl_option CYGNUM_DEVS_FLASH_AMD_AM29XXXXX_V2_ERASE_TIMEOUT {
 	display		"Maximum number of iterations during a block erase"
 	flavor		data
diff -x CVS -x .svn -x .git -x .hg -x '*~' -x '.#*' -x autom4te.cache -urpN packages/devs/flash/amd/am29xxxxxv2/v2_0_92/src/am29xxxxx_aux.c packages/devs/flash/amd/am29xxxxxv2/v2_0_92/src/am29xxxxx_aux.c
--- packages/devs/flash/amd/am29xxxxxv2/v2_0_92/src/am29xxxxx_aux.c	2008-06-04 20:35:23.000000000 +0100
+++ packages/devs/flash/amd/am29xxxxxv2/v2_0_92/src/am29xxxxx_aux.c	2018-11-10 05:15:52.432589091 +0000
@@ -456,6 +456,10 @@ AM29_FNNAME(am29_hw_erase)(volatile AM29
          retries > 0;
          retries--) {
         
+#if CYGNUM_DEVS_FLASH_AMD_AM29XXXXX_V2_ERASE_DELAY > 0        
+        // Some chips want a delay between polling
+        { int j; for( j = 0; j < CYGNUM_DEVS_FLASH_AMD_AM29XXXXX_V2_ERASE_DELAY; j++ ) HAL_REORDER_BARRIER(); }
+#endif
         datum  = addr[AM29_OFFSET_COMMAND];
         // The operation completes when all DQ7 bits are set.
         if ((datum & AM29_STATUS_DQ7) == AM29_STATUS_DQ7) {
diff -x CVS -x .svn -x .git -x .hg -x '*~' -x '.#*' -x autom4te.cache -urpN packages/hal/m68k/mcf52xx/mcf5282/dnp5280/v2_0_92/cdl/hal_m68k_dnp5280.cdl packages/hal/m68k/mcf52xx/mcf5282/dnp5280/v2_0_92/cdl/hal_m68k_dnp5280.cdl
--- packages/hal/m68k/mcf52xx/mcf5282/dnp5280/v2_0_92/cdl/hal_m68k_dnp5280.cdl	2008-05-27 00:08:35.000000000 +0100
+++ packages/hal/m68k/mcf52xx/mcf5282/dnp5280/v2_0_92/cdl/hal_m68k_dnp5280.cdl	2018-11-10 05:04:04.358738997 +0000
@@ -103,6 +103,7 @@ cdl_package CYGPKG_HAL_M68K_DNP5280 {
     # The DNP/528x boards come with a single AM29LV640ML or compatible
     # flash memory device.
     implements      CYGHWR_DEVS_FLASH_AMD_AM29XXXXX_V2_CACHED_ONLY
+    requires        { is_active(CYGPKG_DEVS_FLASH_AMD_AM29XXXXX_V2) implies CYGNUM_DEVS_FLASH_AMD_AM29XXXXX_V2_ERASE_DELAY >= 20 }
     compile     -library=libextras.a dnp5280_extflash.c
 
     # Rev 1.2 modules come with a DS1306 wallclock device accessed via a 3-wire